1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices, particularly to a phase change memory in which the crystalline state changes according to the stored data. More specifically, the present invention relates to the technique for shrinking the components of a phase change memory.
2. Description of the Background Art
A non-volatile memory that stores data in a non-volatile manner is known as one type of a semiconductor memory device. Since data is stored in a non-volatile manner in such a non-volatile memory, data can be retained even if power is cut off. No power supply for data retention is required. Thus, non-volatile memories are widely utilized in various applications such as portable equipment.
As such a non-volatile memory, a magnetic memory that utilizes the magneto-resistance effect is known, in which the magnetic substance has a different resistance depending upon the direction of magnetic polarization. In the magnetic memory disclosed in Japanese Patent Laying-Open No. 2001-266565, for example, a closed magnetic circuit is formed in the memory cell. The direction of polarization of the magnetic element for data storage is set by altering the magnetic flux formed by the closed magnetic circuit according to stored data. In order to establish the direction of the magnetic flux in this closed magnetic circuit, the soft magnetic substance arranged in the closed magnetic circuit is heated to be converted into a paramagnetic substance.
This prior art approach requires the selection of a magnetic flux direction of the closed magnetic circuit corresponding to the stored data. In order to store 1-bit data, two soft magnetic substances must be disposed for the respective magnetic flux directions. Depending on the stored data, one soft magnetic substance is heated to open the closed magnetic circuit while the other soft magnetic substance is employed to set the direction of the magnetic flux formed in the closed magnetic circuit for determining the direction of magnetic polarization of the data storing magnetic element. Since two soft magnetic substances have to be disposed in order to selectively set one of the two magnetic flux directions for each memory cell of one bit, the area occupied by memory cell increases.
As a memory that stores data in a non-volatile manner by altering the physical state of a material, a phase change memory (OUM is known, which is disclosed, for example, in 2002 IEEE ISSCC Digest of Technical Papers 2002 February, pp. 202 to 203. A phase change memory takes advantage of the fact that the resistance change accompanies the change of the crystalline state. Such a phase change memory typically utilized that a chalcogenide layer is different in resistance between an amorphous state and a polycrystalline state. The crystalline state is altered by supplying a current flow to heat the chalcogenide layer by the Joule heat generated by the current for setting the crystalline state of the chalcogenide layer.
FIG. 44 schematically shows the layout of an array in a conventional phase change memory. In FIG. 44, memory cells arranged in three rows and three columns are depicted representatively.
Referring to FIG. 44, word lines WL0–WL2 are disposed corresponding to respective rows of memory cells MC. These word lines WL0–WL2 are each formed of a diffusion layer.
Corresponding to the columns of memory cells MC, bit lines BL0–BL2 are disposed, respectively. A memory cell MC includes a chalcogenide film CG storing data depending upon the crystalline state thereof, and a heater HT for heating the chalcogenide film CG. Although not explicitly depicted in FIG. 44, heater HT is coupled to a corresponding word line WL (WL0 to WL2) via a bipolar transistor.
FIG. 45 schematically shows a sectional structure taken along line 45A—45A shown in FIG. 44. Referring to FIG. 45, an N type impurity layer IMN is formed at the surface of a P type semiconductor substrate region SUB. Th N type impurity layers IMN constitute respective word lines WL0, WL1 and WL2. N type impurity layer IMN is formed continuously extending in the row direction. At the surface of N type impurity layer IMN, a P type impurity region IMP is formed corresponding to a memory cell location. P type impurity region IMP is connected to heater HT. A chalcogenide film CG is formed on and above heater HT. Bit line BL1 is formed extending in the column direction and is connected to chalcogenide film CG. Therefore, chalcogenide films CG of memory cells MC arranged in a column are electrically coupled at each respective one of bit line BL0–BL2.
Memory cell MC is constructed by a chalcogenide film CG, a heater HT, an impurity region IMP and an impurity layer IMN. A vertical PNP bipolar transistor is formed of impurity region IMP, impurity layer IMN and P type semiconductor substrate region SUB. N type impurity layer IMN functions as the base of the bipolar transistor and is set at an L (logical low) level for turning conductive the vertical bipolar transistor formed of impurity region IMP, impurity layer IMN, and semiconductor substrate region SUB.
In a data write mode, current flows from bit line BL (BL1 to BL2) to P type semiconductor substrate region SUB via the bipolar transistor in a conductive state. By the Joule heat at heater HT, chalcogenide film CG is heated, whereby the crystalline state thereof changes. Chalcogenide film CG has its crystalline state altered between an amorphous state and a polycrystalline state. In an amorphous state, chalcogenide film CG is high in resistance, and in general, this state is referred to as “reset state”. In a polycrystalline state, chalcogenide film CG is low in resistance, and this state is referred to as a “set state”.
To set an amorphous state or polycrystalline state, the write current pulse and the current amount are adjusted. In the aforementioned prior art document, the conditions set forth below are employed for writing data. Where chalcogenide film CG is to be set into an amorphous state, a voltage pulse of 0.8 to 0.9V and 8 ns (nano seconds) duration, for example, is applied to bit line BL (BL0–BL2). Where chalcogenide film CG is to be set into a polycrystalline state, a current pulse of approximately 0.5V and 85 ns, for example, is applied to the bit line. By altering the current pulse form according to the write data, chalcogenide film CG can be selectively set into an amorphous state of high resistance and a polycrystalline state of low resistance. The write current is supplied from an internal data line to a bit line via a column select gate.
In data reading, the amount of current flowing through chalcogenide film CG differs depending upon the crystalline state, and accordingly, the amount of current flowing through bit line BL (BL0–BL2) changes. In the aforementioned prior art document, an example is shown where the resistance in the amorphous state is 85 KΩ and the resistance in a crystalline state is 2KΩ. Also, as an example of the structure of the chalcogenide film, a Ge.Sb.Te alloy film is shown. Data is read out by detecting the amount of current flowing through this bit line.
FIG. 46 represents an electrical equivalent circuit of the memory cell arrangement shown in FIG. 44. In FIG. 46, memory cells MC are arranged in three rows and three columns. Memory cell MC includes a variable resistance element VR having a resistance thereof changing according to the stored information, and a transistor element TR rendered conductive, when a corresponding word line WL (WL0–WL2) is selected, to electrically couple a corresponding variable resistance element VR to a collector line CK (CK0–CK2).
Variable resistance element VR is connected to a bit line BL (BL0–BL2) arranged at a corresponding column. Variable resistance element VR includes a chalcogenide film CG and a heater HT shown in FIG. 45. Transistor element TR is formed of impurity region IMP, N type impurity layer IMN and substrate region SUB shown in FIG. 45. Corresponding to each column of memory cells MC, there are arranged collector lines CK0–CK2 each having the collectors of the transistor elements connected. As shown in FIG. 45, these collector lines CK0–CK2 are coupled to semiconductor substrate region SUB, and are each biased to, for example, the ground voltage.
When a memory cell MC located at the crossing between bit line BL1 and word line WL1 is selected in the memory array equivalent circuit of FIG. 46, word line WL1 is set to, for example, an L level of the ground voltage, and unselected word lines WL0 and WL2 are maintained at an H level of the power supply voltage level. In such a state, transistor element TR of memory cell MC is rendered conductive in accordance with the L level signal on word line WL1, and variable resistance element VR is coupled to collector line CK1 (semiconductor substrate region SUB).
In data writing, one of a reset current Irst and a set current Iset for setting the chalcogenide layer in variable resistance element VR to a reset state and a set state, respectively, is supplied to bit line BL1 according to the write state. By this current, current flows from bit line BL1 to collector line CK1 (substrate region) via transistor TR. The heater in variable resistance element VR is heated by the Joule heat, whereby the chalcogenide layer is set to the reset state (amorphous state) or the set state (polycrystalline state).
Unselected bit lines BL0 and BL2 are set at an L level of, for example, the ground voltage. At this stage, even when word line WL1 is in a selected state and the corresponding transistor element TR is rendered conductive, no current flows since the corresponding bit line BL and collector line CK (semiconductor substrate region) are at the same voltage level. Therefore, the resistance of the variable resistance element does not change in the unselected memory cell.
In data reading, a readout current is caused to flow into a selected bit line (for example, BL1). This readout current flows to collector line CK (for example, CK1) via variable resistance element VR and transistor element TR. This bit line current is detected by a sense amplifier in a readout circuit not shown, whereby the memory cell data is read out.
FIG. 47 shows, in more detail, the electrical equivalent circuit of FIG. 46. As already described, word line WL (WL0–WL2) is formed of an impurity layer and is associated with an RC component based on the diffusion resistance and the junction capacitance. In FIG. 47, a diffusion resistance Rpw connected to word line WL2 is depicted as a representative parasitic resistance.
Collector line CK (CK0–CK2) is a semiconductor substrate region, and therefore, collector lines CK0–CK2 are interconnected together. In this case, substrate resistance Rps contributes to the parasitic resistance component. In addition, there is present a parasitic capacitance such as the junction capacitance between the substrate region and the diffusion layer (impurity layer). In FIG. 47, substrate resistance Rps connected to collector line CK0, and a substrate resistance Rps between collector lines CK0 and CK1, and between collector lines CK1 and CK2 are depicted as the representative substrate resistance.
Word line WL cannot be driven to a selected state at high speed by such parasitic RC component. There is a problem that the access time becomes longer.
It is to be noted that transistor element TR in memory cell MC is a bipolar transistor, or is a current driven type transistor. When a potential distribution is generated in a selected word line, the operation characteristics of the transistor element TR included in these memory cells MC will be changed to change the amount of current flowing through the selected memory cell. There is a problem that data writing and reading cannot be performed correctly.
When a potential distribution is generated in collector line CK (CK0–CK2) by substrate resistance Rps, the amount of current flowing from bit line BL (BL0–BL2) to a corresponding collector line CK via transistor element TR of memory cell MC will differ in data writing. Thus, there is a similar problem that data writing and reading cannot be performed accurately.
Particularly, when the memory cell size is shrunk greatly, the entire volume of the chalcogenide layer becomes smaller, the change in resistance corresponding to stored data will become smaller, resulting in a smaller change in current amount. In such a case, the problem of potential distribution on word line WL and collector line CK caused by diffusion resistance Rpw and substrate resistance Rps becomes more severe.
In data writing, the bottom portion of the chalcogenide film included in variable resistance element VR connected to the heater causes phase-change by the heat from the heater. In such arrangement, phase-change does not occur over the entire chalcogenide film. The aforementioned prior art document describes that the volume of the portion that causes phase-change in the chalcogenide film is small, and therefore, the energy required for data writing can be saved to allow reduction of power consumption. Such partial heating serves to prevent the heating from affecting an unselected bit line. However, if the entire chalcogenide film becomes smaller in accordance with miniaturization of memory cells, the resistance cannot be changed sufficiently according to the stored data in the case when phase change is effected at only a portion of the small chalcogenide film. In is difficult to accurately write/read data in such a situation.